1. Field of the Invention
The present invention relates to a method for controlling roughness on the surface of a monocrystal inclusive of flattening the surface of the monocrystal, and more specifically, it relates to a method for controlling roughness on the surface of a semiconductor monocrystal suitable for electronic devices and integrated circuits.
2. Related Background Art
In order to meet requirements of speed up, high performance and high mechanism of devices, various researches and developments mainly such as miniaturization of semiconductors, have been made. Particularly, in recent years, much attention has been paid to researches about the surface state of substrates and grown films due to the development of atomic force microscopy, scanning tunneling microscopy and the like, making the influence of the surface state on the devices apparent. For example, with regard to problems of roughness on the surface of a semiconductor layer, it has been reported that the flatness on the surface of an Si monocrystalline layer affects the mobility of an MOS device [M. Miyashita et al., Extended Abstracts of the 179th Electrochemical Society Meeting, Washington, D.C., pp. 709-710 (1991)], and it also affects the insulating pressure resistance of an oxide film. These problems have a great influence on the scatter of the respective devices owing to the drop of a processing signal level with the miniaturization of a device size.
On the other hand, the researches about the surface state of the monocrystal are important for not only wafers but also porous layers. Particularly in recent years, these porous layers are expected for the realization of SOI structures [FIPO (Full Isolation by Porous Oxidized Silicon)]and for the application as Si light emitting elements, but needless to say, the surface state on the porous layers (inclusive of flatness, pore size and density) and the flatness on the surfaces of the monocrystalline layers deposited on the porous layers have a large influence on physical properties and the devices.
Heretofore, reports regarding the positive improvement of roughness (mainly micro roughness) on the surfaces of Si wafers are restricted, but nowadays, there has been reported that the removal of a spontaneous oxide film and the flattening of the Si surface can be achieved by a cleaning treatment using ultraviolet light excitation F.sub.2 /H.sub.2 (Aoyama et al., the 51st Autumn Applied Physics 28a-D-8, and the 39th Spring Applied Physics 12a-B-6). However, this reported technique has some problems such as an insufficient flattening effect, the presence of RMS (Route Mean Square) of 0.6 nm or more, the employment of troublesome fluorine gas, and the occurrence of chemical reactions which gives rise to surface orientation dependence. In addition, there has been a report that a flattening degree by anneal at a high temperature (1,000.degree. C.) in vacuo in an MBE apparatus was confirmed by an RHEED observation (Sakamoto et al., Electron Communication Society, Technical Report, SSD86-25), a report that in the case of high-temperature anneal in a nitrogen atmosphere, a temperature of 1,000.degree. C. or more is necessary for flattening (Horiuchi et al., Electric Information Communication Society, SDM 91-194), and a report that a surface treatment prior to epitaxial growth is carried out at a temperature of 900.degree. C. or more under reduced pressure in a hydrogen atmosphere (A. Ohkura et al., Extended Abstracts of the 1991 International Conference on SSDM (1991), pp. 559-561). These methods require high temperatures, and therefore applicable substrates are inconveniently limited. Moreover, it has also been reported that the generation of roughness can be inhibited by the irradiation of hydrogen plasma (Ishii et al., the 39th Spring Applied Physics 12a-B-1), but this technique has problems of damage by plasma and an insufficient control effect. It should be noted that these reports intend to prevent the enlargement of the micro roughness rather than to positively eliminate the micro roughness.
On the other hand, much attention is also paid to the control of roughness on a monocrystal surface in addition to the micro roughness, and for example, there is a problem regarding the control of roughness on the surfaces of porous layers. Prior to the description about porous layers, porous Si will be briefly explained. The porous Si has been discovered in the course of the research of electrolytic polishing of a semiconductor in 1956 by Uhlir et al. [A. Uhlir, Bell Syst. Tech. J., Vol. 35, p. 333 (1956)]. Furthermore, Unagami et al. have researched the dissolving reaction of Si in anodization, and they have reported that positive holes are necessary for the anodic reaction of Si in an HF solution [T. Unagami, J. Electrothem. Soc., Vol. 127, p. 476 (1980)]. According to observation through a transmission electron microscope, this porous Si has pores having a diameter of about 600 .ANG. on the average, and the density of these pores is not more than half of that of monocrystal line Si. Nevertheles, the porous Si maintains monocrystal properties, and it is also possible to achieve the epitaxial growth of a monocrystalline Si layer on the porous layer (Unagami, J. Electrochem. Soc., Solid-state Science and Technology, pp. 1339). However, the crystallinity of the grown monocrystalline film is not perfect, and crystal defects are present. When it is attempted to improve the crystallinity by a high-temperature treatment or high-temperature film formation, characteristics of the porous Si sometimes alter, and so the properties themselves of the porous Si such as speeding up oxidation tend to change. In particular, when a temperature of 1,000.degree. C. is used, the rearrangement of the pores in the porous Si occurs inconveniently. That is, it is not easy to grow, on the porous layer, the defects-free monocrystalline Si which is useful at the time of FIPOS formation, does not bring about the property change of the porous layer, and is excellent in flatness at a low temperature. For example, when the epitaxially grown layer is formed, a layer containing many voids is inconveniently grown in the form of an intermediate step [H. Takai et al., J. of Electronic Materials, Vol. 12, p. 973 (1983)], and as described above, crystal defects are formed disadvantageously. On the other hand, although the density of monocrystalline Si is 2.33 g/cm.sup. 3, the density of the above-mentioned porous Si layer can be changed to a value in the range of 1.1 to 0.6 g/cm.sup.3 by altering the concentration of an HF solution to 50-20%. However, for the formation of the porous layer, a wet treatment which is the anodization process is used, and the dependence of a substrate concentration is strong. Thus, many restrictions are present, and so it is difficult to precisely control the thickness of the porous layer, impurities therein and the diameter of the pores therein. For these reasons, many problems must be solved in order to form the desired porous layer. Hence, a growth process is desired which permits the epitaxial growth of a porous layer having pores on the porous layer, the growth of a monocrystalline layer having no pores thereon, and which can optionally control the porosity and the flatness of the porous layer. Particularly, if the above-mentioned problems can be overcome by a dry treatment instead of the wet treatment, the above-mentioned growth process is more preferable, because an adsorbent such as moisture in the porous layer can be excluded.